1. Field of the Invention
The present invention relates to a power supplying circuit and a power supplying method, and particularly relates to a power supplying circuit and a power supplying method that can restrain noise.
2. Description of the Prior Art
High-integrated SOC (System On a Chip) always includes an analog circuit and a digital circuit. However, the noise to the power source, which is generated by the digital circuit, may decreases the performance of the analog circuit. Additionally, the noise to the power source, which is generated by the power amplifier or the switching regulator integrated in the chip, may affect other circuits. Therefore, the stability of power supplying should be seriously concerned if the SOC is desired to have the best performance. Accordingly, the sub circuit of the SOC needs a power regulator to resist the disturbance of the power noise. In view of above-mentioned argument, it is an importance subject to provide a voltage regulator that has low voltage drop but high power noise reduction.
In order to solve above-mentioned problems, some solutions are developed but always have disadvantages hard to be overcome. For example, in the U.S. patent with a U.S. Pat. No. 5,162,668, a charge pump is utilized to increase the power supplying of the high voltage regulator, thereby the voltage drop between the power supplying and the output voltage rises. However, not only the extra circuits increase power consumption and circuit region, the extra clock signals also generate disturbance to other circuits. Also, in the U.S. patent with a U.S. Pat. No. 6,541,946B1, a high pass filter is utilized to add the power supplying noise to a control loop of the voltage regulator. However, low frequency power supplying noise reduction can not be improved since the low frequency noise can not be responded in the control loop of the voltage regulator. If such effect is desired, a large circuit region is necessary. Furthermore, in the U.S. patent with a U.S. Pat. No. 6,897,637B2 and the IEEE paper of S. K. HOON, a voltage subtractor is added to the voltage regulator loop such that the power supplying noise is directly feed backed to the power transistor. However, such mechanism has limited power supplying reduction improvement, according to theoretically inference or actual experiment data, thus does not match high noise reduction requirement for modern SOCs. Moreover, in the IEEE 2010 paper of Mohamed El-Nozahi, a Feed-forward Amplifier is utilized to add a power supplying noise neutralization path. The main disadvantage thereof is that an external capacitor is needed such that the dominant pole is designed outside the chip to maintain the loop stability. However, the cost and PCB (printed circuit board) region accordingly rise, such that the low cost and high integration requirement of the modern SOC can not be matched.